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K4C5608/1638C
256Mb Network-DRAM
256Mb Network-DRAM Specification Version 0.7
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REV. 0.7 Aug. 2003
K4C5608/1638C
Revision History
Version 0.0 (Oct. / 5 / 2001) - First Release Version 0.1 (Dec. / 15 / 2001) - The product name is changed to Network-DRAM Version 0.2 (Jan. / 21 / 2002) - M-version is renamed to C-version - Specify DC operating condition values - Added Power Up Sequence and Power Down(CL=4) Timing Diagrams Version 0.3 (Mar. / 23 / 2002) - The product name is changed to Network RAM - Added Speed bin (366Mbps/pin,183MHz) Version 0.4 (May. / 01 / 2002) - The product name is changed to Network-DRAM - Redefined IDD1S, IDD5 in DC Characteristic Version 0.5 (Nov. /23 / 2002) -Updated the current spec. value Version 0.6 (Apr. /9 / 2003) -Changed IDD2P value from 2mA to 3mA in page 10. -Changed capacitance of DQ/DQS Unit: pF Min Capacitance(DQ/DQS) 4.0 From Max 6.0 Min 3.0 To Max 6.0
256Mb Network-DRAM
Version 0.7 (Aug.31 / 2003) -Changed tCK max like below From D4 8.5 DA 12 D3 12 D4 7.5 To DA 7.5 D3 7.5
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REV. 0.7 Aug. 2003
K4C5608/1638C
General Information
Organization 256Mx8 256Mx16 D4 (400Mbps) K4C560838C-TCD4 K4C561638C-TCD4 DA (366Mbps ) K4C560838C-TCDA K4C561638C-TCDA D3 (333Mbps )
256Mb Network-DRAM
K4C560838C-TCD3 K4C561638C-TCD3
1
2
3
4
5
6
7
8
9
10
11
K 4 C XX XX X X X - X X XX
Memory DRAM Temperature & Power Small Classification Density and Refresh Organization Bank 1. SAMSUNG Memory : K 2. DRAM : 4 3. Small Classification C : Network-DRAM 4. Density & Refresh 56 : 256M 8K/64ms 5. Organization 08 : x8 16 : x16 8. Version C : 4th Generation 9. Package T : TSOP II (400mil x 875mil) 10. Temperature & Power C : (Commercial, Normal) 11. Speed D4 : 400bps/pin (200MHz, CL=4) DA : 366bps /pin (183MHz, CL=4) D3 : 333bps/pin (167MHz, CL=4) Package Version Interface (VDD & VDDQ) Speed
6. Bank 3 : 4 Bank 7. Interface (VDD & VDDQ) 8: SSTL-2(2.5V, 2.5V)
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K4C5608/1638C
Key Feature
Item tCK Clock Cycle Time (Min.) tRC Random Read/Write Cycle Time (Min.) tRAC Random Access Time (Max.) IDD1S Operating Current (Single bank) (Max.) IDD2P Power Down Current (Max.) IDD6 Self-Refresh Current(Max.) CL=3 CL=4
256Mb Network-DRAM
K4C560838/1638C-TC D4 (400Mbps) 5.5ns 5ns 25ns 22ns 310mA 2mA 3mA DA (366Mbps) 6ns 5.5ns 27.5ns 24ns 300mA 2mA 3mA D3 (333Mbps) 6.5ns 6ns 30ns 26ns 290mA 2mA 3mA
* Fully Synchronous Operation Double Data Rate (DDR) Data input/output are synchronized with both edges of DQS. Differential Clock (CK and CK)inputs CS, FN and all address input signals are sampled on the positive edge of CK. Output data (DQs and DQS) is referenced to the crossings of CK and CK. * Fast clock cycle time of 5ns minimum Clock : 200MHz maximum Data : 400Mbps/pin maximum * Quad independent banks operation * Fast cycle and short Iatency * Bidirectional data strobe signal * Distributed Auto-Refresh cycle in 7.8us * Self-Refresh * Power Down Mode * Variable Write Length Control * Write Latency = CAS Latency - 1 * Programmable CAS Latency and Burst Length CAS Latency = 3, 4 Burst Length = 2, 4 * Organization K4C561638C-TC : 4,194,304 words x4 banks x 16 K4C560838C-TC : 8,388,608 words x4 banks x 8 * Power supply voltage Vdd : 2.5 0.15V VddQ : 2.5 0.15V * 2.5V CMOS I/O comply with SSTL-2 (Strong / Normal / Weaker / Weakest) * Package 400X875mil, 66pin TSOP II, 0.65mm pin pitch (TSOP II 66-P-400-0.65)
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K4C5608/1638C
Pin Names
Pin A0 to A14 BA0, BA1 DQ0 to DQ7 (x8) DQ0 to DQ15 (x16) CS FN PD CK, (CK) DQS (X8) Write/Read Data Strobe UDQS/LDQS (X16) Vdd Vss VddQ VssQ VREF NC1,NC2 Power(+2.5V) Ground Power (+2.5V) (for I/O buffer) Ground (for I/O buffer) Reference Voltage No Connection Data Input/Output Chip Select Function Control Power Down Control Clock Input Name Address Input Bank Address Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 NC1 VddQ LDQS NC1 Vdd NC1 NC2 A14 A13 FN CS NC1 BA0 BA1 A10 A0 A1 A2 A3 Vdd Vdd DQ0 VddQ NC2 DQ1 VssQ NC2 DQ2 VddQ NC2 DQ3 VssQ NC2 NC1 VddQ NC2 NC1 Vdd NC1 NC2 A14 A13 FN CS NC1 BA0 BA1 A10 A0 A1 A2 A3 Vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
256Mb Network-DRAM
Pin Assignment (Top View)
K4C561638C-TC K4C560838C-TC
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 Vss DQ7 VssQ NC2 DQ6 VddQ NC2 DQ5 VssQ NC2 DQ4 VddQ NC2 NC1 VssQ DQS NC1 VREF Vss NC2 CK CK PD NC1 A12 A11 A9 A8 A7 A6 A5 A4 Vss Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 NC1 VssQ UDQS NC1 VREF Vss NC2 CK CK PD NC1 A12 A11 A9 A8 A7 A6 A5 A4 Vss
400mil Width 875mil Length
66Pin TSOP II
0.65mm Lead Pitch
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K4C5608/1638C
Package Outline Drawing (TSOP II 66-P-400-0.65)
66
256Mb Network-DRAM
Unit in mm
34
10.16 0.1 1 0.71TYP 0.65 + 0.08 0.24 - 0.07 33 0.13 M 22.22
11.76 0.2 0.145 0.055
0.1
1.2 MAX
1 0.1
22.62 MAX
0.1 0.05
0.1
0.5 0.1 0.8 0.2
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0 ~ 10x
K4C5608/1638C
Block Diagram
CK CK PD DLL CLOCK BUFFER
256Mb Network-DRAM
To Each Block
BANK #3 CS FN COMMAND DECODER CONTROL SIGNAL GENERATOR BANK #2 DATA CONTROL AND LATCH CIRCUIT READ DATA BUFFER WRITE DATA BUFFER DQ BUFFER DQ0 to DQn BANK #1 BANK #0
ROW DECODER
A0 to A14 BA0, BA1
ADDRESS BUFFER
MODE REGISTER
MEMORY CELL ARRAY
UPPER ADDRESS LATCH LOWER ADDRESS LATCH
COLUMN DECODER
REFRESH COUNTER
BURST COUNTER
WRITE ADDRESS LATCH ADDRESS COMPARATOR
DQS
Note : The K4C560838C-TC configuration is 4 Bank of 32768X256X 8 of cell array with the DQ pins numbered DQ0-7 The K4C561638C-TC configuration is 4 BanK of 32768X128X16 of cell array with the DQ pins numbered DQ0-15.
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K4C5608/1638C
Absolute Maximum Ratings
Symbol Vdd VddQ VIN VOUT VREF TOPR TSTG TSOLDER PD IOUT Parameter Power Supply Voltage Power Supply Voltage (for I/O buffer) Input Voltage DQ pin Voltage Input Reference Voltage Operating Temperature Storage Temperature Soldering Temperature(10s) Power Dissipation Short Circuit Output Current Rating -0.3 to 3.3 -0.3 to Vdd + 0.3 -0.3 to Vdd + 0.3
256Mb Network-DRAM
Units V V V V V
O
Notes
-0.3 to VddQ + 0.3 -0.3 to Vdd + 0.3 0 to 70 -55 to 150 260 1 50
C C C
O
O
W mA
Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.
Recommanded DC,AC Operating Conditions (Notes : 1)
Symbol Vdd VddQ VREF VIH (DC) VIL(DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC) Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input Reference Voltage Input DC high Voltage Input DC Low Voltage Differential Clock DC Input Voltage Input Differential Voltage. CK and CK Inputs (DC) Input AC High Voltage Input AC Low Voltage Input Differential Voltage. CK and CK Inputs (AC) Differential AC Input Cross Point Voltage Differential Clock AC Middle Level Parameter Min 2.35 2.35 VddQ/2*96% VREF+0.2 -0.1 -0.1 0.4 VREF+0.35 -0.1 0.7 VddQ/2-0.2 VddQ/2-0.2 Typ 2.5 2.5
(Ta = 0 to 70 xC) Max 2.65 2.65 VddQ/2*104% VddQ+0.2 VREF-0.2 VddQ+0.1 VddQ+0.2 VddQ+0.2 VREF-0.35 VddQ+0.2 VddQ/2+0.2 VddQ/2+0.2 Units V V V V V V V V V V V V 2 5 5 10 7,10 3,6 4,6 7,10 8,10 9,10 Notes
VddQ/2 -
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K4C5608/1638C
256Mb Network-DRAM
Notes: 1. All voltages are referenced to Vss, VssQ. 2. VREF is expected to track variations in VddQ DC level of the transmitting device. Peak to peak AC noise on VREF may not exceed 2% of VREF (DC). 3. Overshoot Iimit : VIH(max.) = VddQ + 0.9V with a pulse width <= 5ns 4. Undershoot Iimit : VIL(min.) = -0.9V with a pulse width <= 5ns 5. VIH(DC) and VIL(DC) are levels to maintain the current logic state. 6. VIH(AC) and VIL(AC) are levels to change to the new logic state. 7. VID is magnitude of the difference between CK input level and CK input level. 8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device. 9. VISO means [VICK(CK) + VICK(CK)]/2 10. Refer to the figure below.
CLK
VX VX VICK VX VX VICK VICK VX VID(AC)
CLK
VICK
VSS VID(AC) 0 V Differential VISO
VISO(min) VISO(max)
VSS 11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of VREF(DC) 0.04V.
Pin Capacitance (Vdd, VddQ = 2.5V, f = 1MHz, Ta = 25xC)
Symbol CIN CINC CI/O CNC1 CNC2 Input Pin Capacitance Clock Pin (CK, CK) Capacitance I/O Pin (DQ, DQS) Capacitance NC1 Pin Capacitance NC2 Pin Capacitance Parameter Min 2.5 2.5 3.0 4.0 Max 4.0 4.0 6.0 1.5 6.0 Units pF pF pF pF pF
Note : These parameters are periodically sampled and not 100% tested. 2 The NC2 pins have additional capacitance for adjustment of the adjacent pin capacitance. 1 The NC2 pins have Power and Ground clamp.
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K4C5608/1638C
256Mb Network-DRAM
Max D4(400Mbps) DA(366Mbps) D3(333Mbps)
DC Characteristics and Operating Conditions (Vdd, VddQ = 2.5V 0.15V, Ta = 0~70xC)
Item
Operating Current tCK = min, IRC=min Read/Write command cycling OV<=VIN<=VIL(AC) (max.) VIH(AC)(min.) <=VIN<=VddQ 1 bank operation, Burst Length = 4 Address change up to 2 times during minimum IRC. Standby Current tCK=min, CS = VIH, PD = VIH, 0V<=VIN<=VIL(AC)(max.) VIH(AC)(min.)<=VIH<=VddQ All Banks : inactive state Other input signals are changed one time during 4*tCK Standby (Power Down) Current tCK=min, CS = VIH, PD = VIL (Power Down) 0V<=VIN<=VddQ All Banks : inactive state Auto-Refresh Current tCK = min, IREFC= min, tREFI = min Auto-Refresh command cycling 0V<=VIN<=VIL(AC) (max.), VIH(AC) (min.) <=VIN<=VddQ Address change up to 2 times during minimum IREFC. Self-Refresh Current self-Refresh mode PD = 0.2V, OV<=VIN<=VddQ
Symbol
Units
Notes
IDD1S
310
300
290
1, 2
IDD2N
85
85
80
1
mA IDD2P 2 2 2 1
IDD5
105
100
95
1
IDD6
3
3
3
Item
Input Leakage Current (0V<=VIN<=VddQ, All other pins not under test = 0V) Output Leakage Current (Output disabled, 0V<=VOUT<=VddQ) VREF Current Output Source DC Current VOH = VddQ - 0.4V Output Sink DC Current VOL=0.4V Output Source DC Current VOH = VddQ - 0.4V Output Sink DC Current VOL=0.4V Output Source DC Current VOH = VddQ - 0.4V Output Sink DC Current VOL=0.4V Output Source DC Current VOH = VddQ - 0.4V Output Sink DC Current VOL=0.4V
Symbol
ILI ILO IREF IOH(DC) IOL(DC) IOH(DC) IOL(DC) IOH(DC) IOL(DC) IOH(DC) IOL(DC)
Min
-5 -5 -5 -10 10 -11 11 -8 8 -7 7
Max
5 5 5 -
Unit
uA uA uA
Notes
3 3 3 3 mA 3 3 3 3
Normal Output Driver
Strong Output Driver
-
Weaker Output Driver
Weakest Output Driver
Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK, tRC and IRC. 2. These parameters depend on the output loading. The specified values are obtained with the output open. 3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
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K4C5608/1638C
AC Characteristics and Operating Conditions (Notes : 1, 2)
Symbol
tRC tCK tRAC tCH tCL tCKQS tQSQ tAC tOH tQSPRE tHP tQSP tQSQV tDQSS tDSPRE
Random Cycle Time CL = 3 Clock Cycle Time CL = 4 Random Access Time Clock High Time Clock Low Time DQS Access Time from CLK Data Output Skew from DQS Data Access Time from CLK Data Output Hold Time from CLK DQS(Read) Preamble Pulse Width CLK half period ( minium of Actual tCH, tCL) DQS(Read) Pulse Width Data Output Valid Time from DQS DQS(Write) Low to High Setup Time DQS(Write) Preamble Pulse Width 5 0.45*tCK 0.45*tCK -0.65 -0.65 -0.65 0.9*tCK-0.2 min(tCH, tCL) 7.5 22 0.65 0.4 0.65 0.65 1.1*tCK+0.2 1.25*tCK 0.55*tCK 0.5*tCK 0.65 0.65 1 5 5.5 0.45*tCK 0.45*tCK -0.75 -0.75 -0.75
256Mb Network-DRAM
D4(400Mbps) Min
25 5.5
Item
DA(366Mbps) Min
27.5 6
D3(333Mbps) Min
30 6.5 6 0.45*tCK 0.45*tCK -0.85 -0.85 -0.85 0.9*tCK-0.2 min(tCH, tCL)
Max
7.5
Max
7.5 7.5 24 0.75 0.45 0.75 0.75 1.1*tCK+0.2 -
Max
7.5 7.5 26 0.85 0.5 0.85 0.85 1.1*tCK+0.2 1.25*tCK 0.55*tCK 0.5*tCK 0.85 0.85 1 5
Units Notes
3 3 3 3 3 3 3, 8 4 3, 8 3, 8 3
0.9*tCK-0.2 min(tCH, tCL)
tHP-0.55 tHP-0.55
0.75*tCK 0.4*tCK 0 0.25*tCK 0.45*tCK CL = 3 1.3 1.3 0.45*tCK CL = 3 CL = 4 1.3 1.3 -0.5*tCK 0.5 0.5 1.5 0.9 0.9 2.0 -0.65 -0.65 -0.65 0 2 0.1 -0.5*tCK
tHP-0.6 tHP-0.6
0.75*tCK 0.4*tCK 0 0.25*tCK 0.45*tCK 1.4 1.4 0.45*tCK 1.4 1.4 -0.5*tCK 0.5 0.5 1.5 0.9 0.9 2.0 -0.75 -0.75 -0.75 0 2 0.1 -0.5*tCK
tHP-0.65 tHP-0.65
4 4 3 4 3 3 4 ns 3, 4 3, 4 4 3, 4 3, 4
1.25*tCK 0.55*tCK -
0.75*tCK 0.4*tCK 0 0.25*tCK 0.45*tCK 1.5 1.5 0.45*tCK
tDSPRES DQS First Input Setup Time tDSPREH DQS First Low Input Hold Time tDSP tDSS tDSPST
DQS High or Low Input Pulse Width DQS Input Falling Edge to Clock Setup Time CL = 4 DQS(Write) Postamble Pulse Width
tDSPSTH DQS(Write) Postamble Hold Time tDSSK tDS tDH tDIPW tIS tIH tIPW tLZ tHZ tQSLZ tQSHZ tQPDH tPDEX tT tFPDL
UDQS - LDQS Skew (x16) Data Input Setup Time from DQS Data Input Hold Time from DQS Data Input pulse Width (for each device) Command / Address Input Setup Time Command / Address Input Hold Time
0.5*tCK 0.75 0.75 1 5
1.5 1.5 -0.5*tCK 0.6 0.6 1.9 1 1 2.2 -0.85 -0.85 -0.85 0 2 0.1 -0.5*tCK
4 4
3 3
Command / Address Input Pulse Width (for each device) Data-out Low Impedance Time from CLK Data-out High Impedance Time from CLK DQS-out Low Impedance Time from CLK DQS-out High Impedance Time from CLK Last Output to PD High Hold Time Power Down Exit Time Input Transition Time PD Low Input Window for Self-Refresh Entry
3, 6, 8 3, 7, 8 3, 6, 8 3, 7, 8
3
3
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K4C5608/1638C
D4(400Mbps) Min
0.4 200 CL = 3 CL = 4 5 5 1 CL = 3 CL = 4 4 4 2 BL = 2 BL = 4 2 3 1 CL = 3 Mode Register Set Cycle Time CL = 4 PD Low to Inactive State of Input Buffer PD High to Active State of Input Buffer CL = 3 Power down mode valid from REF command CL = 4 CL = 3 Auto-Refresh Cycle Time CL = 4 REF Command to Clock Input Disable at Self-Refresh Entry DLL Lock-on Time (Applicable to RDA command) 18 16 200 18 16 200 18 15 18 15 5 15 1 1 5 15 5
256Mb Network-DRAM
DA(366Mbps) Min
0.4 200 5 5 1 4 4 2 2 3 1 5
AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)
Symbol
tREFI tPAUSE IRC IRCD IRAS IRBD IRWD IWRD IRSC IPD IPDA IPDV IREFC ICKD ILOCK
Item
Auto-Refresh Average Interval Pause Time after Power-up Random Read/Write Cycle Time (Applicable to Same Bank) RDA/WRA to LAL Command Input Delay (Applicable to Same Bank) LAL to RDA/WRA Command Input Delay (Applicable to Same Bank) Random Bank Access Delay (Applicable to Other Bank) LAL following RDA to WRA Delay (Applicable to Other Bank) LAL following WRA to RDA Delay (Applicable to Other Bank)
D3(333Mbps) Min
0.4 200 5 5 1 4 4 2 2 3 1 5 5 15 18 15 18 16 200
Max
7.8 1 -
Max
7.8 1 1 1 -
Max
7.8
Units Notes
5 us
1 Cycle 1 1 -
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K4C5608/1638C
AC Test Conditions
Symbol VIH(min) VIL (max) VREF VTT VSWING VR VID(AC) SLEW VOTR Parameter Input high voltage (minimum) Input low voltage (maximum) Input reference voltage Termination voltage Input signal peak to peak swing Differential clock input reference level Input differential voltage Input signal minimum slew rate Output timing measurement reference voltage VddQ
256Mb Network-DRAM
Value VREF + 0.35 VREF - 0.35 VddQ/2 VREF 1.0 VX(AC) 1.5 1.0 VddQ/2 Units V V V V V V V V/ns V VTT Measurement Point VIH min(AC) Output Z=50 VIL max(AC) CL=30pF VREF
=0.5*VddQ
Notes
RT=50
VSWING
VREF
Vss T T
Output Load Circuit(SSTL_2)
Slew=(VIHmin(AC) - VILmax(AC))/T
Notes : 1. Transition times are measured between VIH min(DC) and VIL max(DC). Transition (rise and fall) of input signals have a fixed slope. 2. If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 0.75*tCK, tCK = 5ns, 0.75*5ns = 3.75ns is rounded up to 3.8ns.) 3. These parameters are measured from the differential clock (CK and CK) AC cross point. 4. These parameters are measured from signal transition point of DQS crossing VREF level. 5. The tREFI (MAX.) applies to equally distributed refresh method. The tREFI (MIN.) applies to both burst refresh method and distributed refresh method. In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the maximum. 6. Low Impedance State is speified at VddQ/2 0.2V from steady state. 7. High Impedance State is specified where output buffer is no longer driven. 8. These parameters depend on the clock jitter. These parameters are measured at stable clock.
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K4C5608/1638C
Power Up Sequence
256Mb Network-DRAM
1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection. 2. Apply Vdd before or at the same time as VddQ. 3. Apply VddQ before or at the same time as VREF. 4. Start clock (CK, CK) and maintain stable condition for 200us (min.). 5. After stable power and clock, apply DESL and take PD = H. 6. Issue EMRS to enable DLL and to define driver strength. (Note : 1) 7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1) 8. Issue two or more Auto-Refresh commands. (Note:1) 9. Ready for normal operation after 200 clocks from Extended Mode Register programming. (Note : 2) Note : 1. Sequence 6, 7 and 8 can be issued in random order. 2. L=Logic Low, H = Logic High
2.5V(TYP)

VDD
2.5V(TYP)

VDDQ
1.25V(TYP)

VREF CLK CLK
200 s(min)
tPDEX tPDA lRSC

lRSC
lREFC

lREFC

PD

200 clock cycle(min)

Command
DESL
RDA MRS
DESL
RDA MRS
DESL
WRA REF
DESL
WRA REF
DESL
op-code
op-code

Address
EMRS
MRS

DQ
Hi-Z

DQS
EMRS
MRS
Auto Refresh cycle
Nomal Operation
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Basic Timing Diagrams
Input Timing
tCK tCK
256Mb Network-DRAM
tCH
tCL
CK
~
CK
tIS tIH 1st tIPW tIS tIH 1st tIS 2nd tIPW tIS tIH UA, BA tIPW tIS LA tIH tIH tIS 2nd tIH
~~ ~
CS
~~ ~~
FN
~~ ~~
A0-A14 BA0.BA1
~
DQS
tDS tDH tDS tDH
~~
DQ(Input)
tDIPW tDIPW
Refer to the Command Truth Table.
Timing of the CK, /CK
tCH tCL VIH VIH(AC) VIL(AC) VIL
CK CK
tCK tT tT
CK CK
VX VX VX
VIH VID(AC) VIL
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K4C5608/1638C
Read Timing (Burst Length = 4)
tCH tCL tCK
256Mb Network-DRAM
CK CK
tIS tIH
Input (Control & Addresses)
LAL
(after RDA)
tIPW
tCKQS tQSLZ tQSPRE tCKQS tQSP
tCKQS tQSP tQSHZ
CAS latency = 3 DQS (Output)
High-Z
High-Z
tQSQV tQSQ tQSQ tQSQV
Preamble tLZ
Postamble tQSQ tHZ
DQ (Output)
High-Z
Q0
tAC
Q1
tAC
Q2
tAC tCKQS
Q3
High-Z
tOH tCKQS tQSP tQSP tQSHZ
CAS latency = 4 DQS (Output)
High-Z
tQSLZ tQSPRE
tCKQS
Preamble tLZ
tQSQ
tQSQV tQSQ tQSQV
Postamble tQSQ tHZ
DQ (Output)
High-Z
Q0
tAC
Q1
tAC
Q2
tAC
Q3
tOH
Note : The correspondence of LDQS, UDQS to DQ. (K4C561638C-TC) LDQS UDQS DQ0 to 7 DQ8 to 15
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Write Timing (Burst Length = 4)
tCH tCL tCK
256Mb Network-DRAM
CK CK
tIS tIH LAL
(after WRA)
Input (Control & Addresses) CAS latency = 3 DQS (Input)
tIPW tDSPRES
tDSPSTH tDQSS tDSP tDSPREH Preamble tDSPRE tDS tDIPW tDH Postamble tDSP tDSP tDSS tDSPST
tDSS tDS
tDS
tDH
tDH
DQ (Input)
D0
D1
tDQSS
D2
D3
tDSS tDSS tDSPSTH tDSP tDSPST
CAS latency = 4 DQS (Input)
tDSPRES tDSPREH Preamble tDSPRE tDS
tDSP
tDSP
tDSS tDIPW tDH tDS
tDS
Postamble
tDH
tDH
DQ (Input)
tDQSS
D0
D1
tDQSS
D2
D3
Note. The correspondence of LDQS, UDQS to DQ. (K4C561638C-TC) LDQS UDQS DQ0 to 7 DQ8 to 15
tREFI, tPAUSE, Ixxxx Timing
CK CK
tIS tIH
tREFI,tPAUSE,IXXXX
~
tIS
tIH
Input (Control & Addresses)
Command
~
Command
Note. "IXXXX"means "IRC", "IRCD", "IRAS", etc.
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Write Timing (x16 device) (Burst Length = 4)
CK CK Input (Control & Addresses) CAS latency = 3 LDQS
Preamble tDH tDS
256Mb Network-DRAM
WRA
LAL
tDSSK
tDSSK
tDSSK
tDSSK
Postamble tDH tDS tDS tDH tDS tDH
DQ0 ~ 7
D0
D1
D2
D3
UDQS
Preamble tDH tDS tDS tDH tDS tDH tDS Postamble tDH
DQ8 ~ 15 CAS latency = 4 LDQS
D0
D1
D2
D3
tDSSK
tDSSK
tDSSK
tDSSK
Preamble tDH tDS tDS tDH tDS tDH tDS
Postamble tDH
DQ0 ~ 7
D0
D1
D2
D3
UDQS
Preamble tDH tDS tDS tDH tDS tDH tDS Postamble tDH
DQ8 ~ 15
D0
D1
D2
D3
- 18 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Function Truth Table (Notes : 1,2,3)
Command Truth Table (Notes : 4)
*The First Command
Symbol DESL RDA WRA Function Device Deselect Read with Auto-close Write with Auto-close CS H L L FN X H L BA1-BA0 X BA BA
256Mb Network-DRAM
A14-A9 X UA UA
A8 X UA UA
A7 X UA UA
A6-A0 X UA UA
*The Second Command (The next clock of RDA or WRA command)
Symbol LAL LAL REF MRS Function Lower Address Latch (x16) Lower Address Latch (x8) Auto-Refresh Mode Register Set CS H H L L FN X X X X BA1-BA0 X X X V A14-A13 A12-A11 V V X L V X X L A10-A9 X X X L A8 X X X L A7 X LA X V A6-A0 LA LA X V
Notes : 1. L = Logic Low, H = Logic High, X = either L or H, V = Valid (Specified Value), BA = Bank Address, UA = Upper Address, LA = Lower Address. 2. All commands are assumed to issue at a valid state. 3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where CLK goes to High. 4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the command table below.
Read Command Table
Command (Symbol) RDA (1st) LAL (2nd) Notes : 5. For x16 device, A7 is "X" (either L or H). CS L H FN H X BA1-BA0 BA X A14-A9 UA X A8 UA X A7 UA LA A6-A0 UA LA 5 Notes
- 19 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Write Command Table
K4C561638C-TC
Command (Symbol) WRA (1st) LAL (2nd) CS L H FN L X BA1-BA0 BA X A14 UA LVWO A13 UA LVW1 A12 UA UVW0
256Mb Network-DRAM
A11 UA UVW1
A10-A9 UA X
A8 UA X
A7 UA X
A6-A0 UA LA
K4C560838C-TC
Command (Symbol) WRA (1st) LAL (2nd) CS L H FN L X BA1-BA0 BA X A14 UA VWO A13 UA VW1 A12 UA X A11 UA X A10-A9 UA X A8 UA X A7 UA LA A6-A0 UA LA
Note : 6. A14 to A11 are used for variable Write Length (VW) control at Write Operation.
VW Truth Table
Function Write All Words BL = 2 Write First One Word Reserved Write All Words BL = 4 Write First Two Words Write First One Word L H H H H L H X L L VW0 L VW1 X
Note : 7. For x16 device, LVW0 and LVW1 control DQ0-DQ7, UVW0 and UVW1 control DQ8-DQ15.
Mode Register Set Command Truth Table
Command (Symbol) RDA (1st) MRS (2nd) CS L L FN H X BA1-BA0 X V A14-A9 X L A8 X L A7 X V A6-A0 X V 8 Notes
Note : 8. Refer to "Mode Register Table".
- 20 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Function Truth Table (Continued)
Auto-Refresh Command Table
Function Active Auto-Refresh Command (Symbol) WRA(1st) REF(2nd) Current State Standby Active PD CS n-1 H H n H H L L L X X X FN
256Mb Network-DRAM
BA1-BA0 A14-A9 X X
A8 X X
A7 X X
A6-A0 X X
Notes
Self-Refresh Command Table
Function Active Self-Refresh Entry Self-Refresh Continue Self-Refresh Exit Command (Symbol) WRA(1st) REF(2nd) SELFX Current State Standby Active Self-Refresh Self-Refresh PD CS n-1 H H L L n H L L H L L X H L X X X X X X X X X X X X X X X X X X X X X X X 11 9, 10 FN BA1-BA0 A14-A9 A8 A7 A6-A0 Notes
Power Down Table
Function Power Down Entry Power Down Continue Power Down Exit Command (Symbol) PDEN PDEX Current State Standby Power Down Power Down PD CS n-1 H L L n L L H H X H X X X X X X X X X X X X X X X X X X 11 10 FN BA1-BA0 A14-A9 A8 A7 A6-A0 Notes
Notes : 9. PD has to be brought to Low within tFPDL from REF command. 10. PD should be brought to Low after DQ's state turned high impedance. 11. When PD is brought to High from Low, this function is executed asynchronously.
- 21 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Function Truth Table (Continued)
Current State PD n-1 H H H H H L H H H H L H H H H L H H H H H L H H H H H L H H H H H L H H H H H L H L L L H L L L n H H H L L X H H L L X H H L L X H H H L L X H H H L L X H H H L L X H H H L L X X L H H X L H H CS H L L H L X H L H L X H L H L X H L L H L X H L L H L X H L L H L X H L L H L X X X H L X X H L FN X H L X X X X X X X X X X X X X X H L X X X X H L X X X X H L X X X X H L X X X X X X X X X X X Address X BA, UA BA, UA X X X LA Op-Code X X X LA X X X X X BA, UA BA, UA X X X X BA, UA BA, UA X X X X BA, UA BA, UA X X X X BA, UA BA, UA X X X X X X X X X X X Command DESL RDA WRA PDEN LAL MRS/EMRS PDEN REF (Self) LAL REF PDEN REF (Self) DESL RDA WRA PDEN DESL RDA WRA PDEN DESL RDA WRA PDEN DESL RDA WRA PDEN RDEX SELFX -
256Mb Network-DRAM
Action NOP Row activate for Read Row activate for Write Power Down Entry Illegal Refer to Power Down state Begin read Access to Mode Register Illegal Illegal Invalid Begin Write Auto-Refresh Illegal Self-Refresh entry Invalid Continue burst read to end Illegal Illegal Illegal Illegal Invalid Data write & continue burst write to end Illegal Illegal Illegal Illegal Invalid NOP-> Idle after IREFC Illegal Illegal Self-Refresh entry Illegal Refer to Self-Refreshing state Nop-> Idle after IRSC Illegal Illegal Illegal Illegal Invalid Invalid Maintain Power Down Mode Exit Power Down Mode->Idle after tPDEX Illegal Invalid Maintain Self-Refresh Exit Self-Refresh->Idle after IREFC Illegal 13 13 Notes
Idle
12
Row Active for Read
Row Active for Write
Read
13 13
Write
Auto-Refreshing
Mode Register Accessing
14
Power Down
Se;f-Refreshing
Notes : 12. Illegal if any bank is not idle. 13. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA). 14. Illegal if tFPDL is not satisfied.
- 22 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Mode Register Table
Regular Mode Register (Notes : 1)
Address Register BA1*1 0 BA0*1 0 A14-A8 0 A7*3 TM
256Mb Network-DRAM
A6-A4 CL
A3 BT
A2-A0 BL
A7 0 1
Test Mode (TM) Regular (Default) Test Mode Entry
A3 0 1
Burst Type (BT) Sequential Interleave
A6 0 0 0 1 1 1
A5 0 1 1 0 0 1
A4 X 0 1 0 1 X
CAS Latency (CL) Reserved *2 Reserved *2 3 4 Reserved *2 Reserved *2
A2 0 0 0 0 1
A1 0 0 1 1 X
A0 0 1 0 1 X
Burst Length (BL) Reserved *2 2 4 Reserved *2
Extended Mode Register (Notes : 4)
Address Register BA1*4 0 BA0*4 1 A14-A7 0 A6 DIC A5-A2 0 A1 DIC A0 DS
A6 0 0 1 1
A1 0 1 0 1
Output Driver Impedance Control (DIC) Normal Output Driver Strong Output Driver Weaker Output Driver Weakest Output Driver
Note : 1. Regular Mode Register is Chosen Using the combination of BA0 = 0 and BA1 = 0. 2. "Reserved" places in Regular Mode Register should not be set. 3. A7 in Regular Mode Register must be set to "0"(Low state). Because test Mode is specific mode for supplier. 4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0.
A0 0 1
DLL Switch (DS) DLL Enable DLL Disable
- 23 -
REV. 0.7 Aug. 2003
K4C5608/1638C
State Diagram
Self Refresh
256Mb Network-DRAM
SELFX (PD = H)
PDEX (PD = H) PDEN (PD = L) Standby (Idle)
Power Down
PD = L PD = H AutoRefresh WRA RDA
Mode Register
REF
MRS
Active (Restore)
Active
LAL
LAL
Write (Buffer)
Read
Command Input Automatic Return The second command at Active state must be issued 1clock after RDA or WRA command input
- 24 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Timing Diagrams
Single Bank Read Timing (CL = 3)
0 CK CK
IRC = 5 cycles
256Mb Network-DRAM
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles
Command
RDA
LAL
DESL
RDA
LAL
DESL
RDA
LAL
BL = 2 DQS (Output)
IRCD = 1 cycle Hi-Z
IRAS = 4 cycles
IRCD = 1 cycle Hi-Z
IRAS = 4 cycles Hi-Z
CL = 3
CL = 3
DQ (Output) BL = 4 DQS (Output)
Hi-Z
Q0 Q1
Hi-Z
Q0 Q1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CL = 3
CL = 3
DQ (Output)
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
Single Bank Read Timing (CL = 4)
0 CK CK
IRC = 5 cycles IRC = 5 cycles
1
2
3
4
5
6
7
8
9
10
11
Command
RDA
LAL
DESL
RDA
LAL
DESL
RDA
LAL
BL = 2 DQS (Output)
IRCD = 1 cycle Hi-Z
IRAS = 4 cycles
IRCD = 1 cycle
IRAS = 4 cycles Hi-Z
CL = 4
CL = 4
DQ (Output) BL = 4 DQS (Output)
Hi-Z
Q0 Q1
Hi-Z
Q0 Q1
Hi-Z
Hi-Z
CL = 4
CL = 4
DQ (Output)
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
Q0 Q1 Q2
- 25 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Single Bank Write Timing (CL = 3)
0 CK CK
IRC = 5 cycles
256Mb Network-DRAM
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles
Command BL = 2 DQS (Input)
WRA
LAL
DESL
IRAS = 4 cycles
WRA
LAL
DESL
IRAS = 4 cycles
WRA
LAL
IRCD = 1 cycle
IRCD = 1 cycle
IRCD = 1 cycle
tDQSS WL = 2 WL = 2
DQ (input)
tDQSS
D0 D1
D0 D1
tDQSS
BL = 4 DQS (Input)
WL = 2 WL = 2
DQ (input)
D0 D1 D2 D3
D0 D1 D2 D3
Single Bank Write Timing (CL = 4)
0 CK CK
IRC = 5 cycles IRC = 5 cycles
1
2
3
4
5
6
7
8
9
10
11
Command BL = 2 DQS (Input)
WRA
LAL
DESL
IRAS = 4 cycles
WRA
LAL
DESL
IRAS = 4 cycles
WRA
LAL
IRCD = 1 cycle
IRCD = 1 cycle
IRCD = 1 cycle
WL = 3
WL = 3
DQ (input)
tDQSS
D0 D1
tDQSS
D0 D1
BL = 4 DQS (Input)
WL = 3 WL = 3
DQ (input)
Note : means "H" or "L"
D0 D1 D2 D3
D0 D1 D2 D3
- 26 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Single Bank Read-Write Timing (CL = 3)
0 CK CK
IRC = 5 cycles
256Mb Network-DRAM
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles
Command
RDA
LAL
DESL
WRA
LAL
DESL
RDA
LAL
BL = 2 DQS
IRCD = 1 cycle Hi-Z
IRAS = 4 cycles
IRCD = 1 cycle Hi-Z
IRAS = 4 cycles Hi-Z
CL = 3
WL = 2
DQ BL = 4 DQS
Hi-Z
Q0 Q1
Hi-Z tDQSS
D0 D1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CL = 3
WL = 2
DQ
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
D0 D1 D2 D3
Hi-Z
Single Bank Read-Write Timing (CL = 4)
0 CK CK
IRC = 5 cycles IRC = 5 cycles
1
2
3
4
5
6
7
8
9
10
11
Command
RDA
LAL
DESL
WRA
LAL
DESL
RDA
LAL
BL = 2 DQS
IRCD = 1 cycle Hi-Z
IRAS = 4 cycles
IRCD = 1 cycle
IRAS = 4 cycles Hi-Z Hi-Z
CL = 4
WL = 3
DQ BL = 4 DQS
Hi-Z
Q0 Q1
Hi-Z
D0 D1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CL = 4
WL = 3
DQ
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
D0 D1 D2 D3
Hi-Z
- 27 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Multiple Bank Read Timing (CL = 3)
0 CK CK
IRC = 5 cycles IRBD = 2 cycles
256Mb Network-DRAM
1
2
3
4
5
6
7
8
9
10
11
IRCD = 1 cycle
IRCD = 1 cycle
Command
RDAa
LALa
RDAb
LALb
DESL
RDAa
LALa
RDAc
LALc
IRBD = 2 cycles
RDAd
LALd
IRBD = 2 cycles
RDAb
IRCD = 1 cycle
IRAS = 4 cycles
IRCD = 1 cycle
Bank Add. (BA0, BA1) BL = 2 DQS (Output) DQ (Output) BL = 4 DQS (Output) DQ (Output)
Bank"a"
X
Bank"b"
X
Bank"a"
X
Bank"c"
X
Bank"d"
X
Bank"b"
IRBD = 2 cycles Hi-Z CL = 3 Hi-Z Hi-Z CL = 3
Qa0 Qa1
CL = 3
Hi-Z
Qb0 Qb1
Hi-Z
Qa0 Qa1
CL = 3
Hi-Z
Qc0
Hi-Z CL = 3 Hi-Z CL = 3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Hi-Z
Qa0 Qa1 Qa2 Qa3 Qc0
Multiple Bank Read Timing (CL = 4)
0 CK CK
IRC = 5 cycles IRBD = 2 cycles IRCD = 1 cycle IRCD = 1 cycle
1
2
3
4
5
6
7
8
9
10
11
Command
RDAa
LALa
RDAb
LALb
DESL
RDAa
LALa
RDAc
LALc
IRBD = 2 cycles
RDAd
LALd
IRBD = 2 cycles
RDAb
IRCD = 1 cycle
IRAS = 4 cycles
IRCD =1 cycle
Bank Add. (BA0, BA1) BL = 2 DQS (Output) DQ (Output) BL = 4 DQS (Output) DQ (Output)
Bank"a"
X
Bank"b"
X
Bank"a"
X
Bank"c"
X
Bank"d"
X
Bank"b"
IRBD = 2 cycles Hi-Z CL = 4 Hi-Z Hi-Z CL = 4
Qa0 Qa1
CL = 4
Hi-Z
Qb0 Qb1
Hi-Z
Qa0 Qa1
CL = 4
Hi-Z
Hi-Z CL = 4 Hi-Z CL = 4
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Hi-Z
Qa0 Qa1 Qa2
Note : "X" is don't care. IRC to the same bank must be satisfied.
- 28 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Multiple Bank Write Timing (CL = 3)
0 CK CK Command WRAa LALa
IRC = 5 cycles IRBD = 2 cycles
256Mb Network-DRAM
1
2
3
4
5
6
7
8
9
10
11
IRCD = 1 cycle
IRCD = 1 cycle
WRAb
LALb
DESL
WRAa
LALa
WRAc
LALc
IRBD = 2 cycles
WRAd
LALd
IRBD = 2 cycles
WRAb
IRCD = 1 cycle
IRAS = 4 cycles
IRCD = 1 cycle
Bank Add. (BA0, BA1) BL = 2 DQS (input)
Bank"a"
X
Bank"b"
X
tDQSS
Bank"a"
X
Bank"c"
X
Bank"d"
X
Bank"b"
IRBD = 2 cycles
tDQSS WL = 2 WL = 2
DQ (input) BL = 4 DQS (input)
Da0 Da1
tDQSS
Db0 Db1
tDQSS
Da0 Da1
tDQSS
Dc0 Dc1
WL = 2
WL = 2
DQ (input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Dc0 Dc1 Dc2
Multiple Bank Write Timing (CL = 4)
0 CK CK Command WRAa LALa
IRC = 5 cycles IRBD = 2 cycles IRCD = 1 cycle IRCD = 1 cycle
1
2
3
4
5
6
7
8
9
10
11
WRAb
LALb
DESL
WRAa
LALa
WRAc
LALc
IRBD = 2 cycles
WRAd
LALd
IRBD = 2 cycles
WRAb
IRCD = 1 cycle
IRAS = 4 cycles
IRCD = 1 cycle
Bank Add. (BA0, BA1) BL = 2 DQS (input)
Bank"a"
X
Bank"b"
X
Bank"a"
tDQSS
X
Bank"c"
X
Bank"d"
X
Bank"b"
IRBD = 2 cycles
tDQSS WL = 3 WL = 3
DQ (input) BL = 4 DQS (input)
Da0 Da1
tDQSS
Db0 Db1
tDQSS
Da0 Da1
tDQSS
Dc0 Dc1
WL = 3
WL = 3
DQ (input)
Note :
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Dc0 Dc1
means "H" or "L" "X" is don't care IRC to the same bank must be satisfied.
- 29 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Multiple Bank Read-Write Timing (BL = 2)
0 CK CK
IRBD = 2 cycles IRCD = 1 cycle IRWD = 2 cycles IRBD = 2 cycles
256Mb Network-DRAM
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles
IRWD = 2 cycles
Command
WRAa
LALa
RDAb
LALb
DESL
WRAc
LALc
RDAd
LALd
DESL
WRAc
LALc
IRCD = 1 cycle
IWRD = 1 cycle
IRCD = 1 cycle
IWRD = 1 cycle
IRCD = 1 cycle
Bank Add. (BA0, BA1) CL = 3 DQS
Bank"a"
Hi-Z
X
Bank"b"
tDQSS
X
Bank"c"
Hi-Z
X
Bank"d"
tDQSS
X
Bank"c"
Hi-Z
X
WL = 2 Hi-Z
CL = 3
WL = 2
CL = 3
DQ CL = 4
Hi-Z
Da0 Da1
tDQSS Hi-Z
Qb0 Qb1
Dc0 Dc1
tDQSS Hi-Z
Qd0
DQS
WL =3 CL = 4 Hi-Z WL = 3 Hi-Z CL = 4
DQ
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Multiple Bank Read-Write Timing (BL = 4)
0 CK CK
IRBD = 2 cycles IRCD = 1 cycle IRWD = 3 cycles IRBD = 2 cycles IRCD = 1 cycle
1
2
3
4
5
6
7
8
9
10
11
Command
WRAa
LALa
RDAb
LALb
DESL
WRAc
LALc
RDAd
LALd
DESL
IRCD = 1 cycle
IWRD = 1 cycle
IRCD = 1 cycle IWRD = 1 cycle
Bank Add. (BA0, BA1) CL = 3 DQS
Bank"a"
Hi-Z
X
Bank"b"
tDQSS
X
Bank"c"
X
Bank"d"
tDQSS
X
WL = 2 Hi-Z
CL = 3 Hi-Z
WL = 2
CL = 3 Hi-Z
DQ CL = 4 DQS
Hi-Z
Da0 Da1 Da2 Da3
tDQSS
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
tDQSS
WL = 3 Hi-Z
CL = 4
WL = 3
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Note : "X" is dont care IRC to the same bank must be satisfied.
- 30 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Single Bank Write with VW (CL=3, BL=4, Sequential mode)
0 CK CK
IRC = 5 cycles
256Mb Network-DRAM
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles
x8 device Command WRA LAL DESL WRA LAL DESL WRA LAL
Address
UA
LA=#3 VW=2
UA
LA=#1 VW=1
UA
LA
DQS (Input) Last two data are masked. DQ (Input) Address x16 device Command WRA LAL DESL WRA LAL DESL WRA LAL D0 D1 #3 #0 (#1) (#2) D0 #1 (#2) (#3) (#0) Last three data are masked.
Address
UA
LA=#3 UVW=2 LVW=1
UA
LA=#3 UVW=1 LVW=1
UA
LA
UDQS (Input) Last two data are masked. DQ8 to DQ15 (Input) Address LDQS (Input) Last three data are masked. DQ0 to DQ7 (Input) Address D0 #3 (#0) (#1) (#2) D0 #1 (#2) (#3) (#0) Last three data are masked. D0 D1 #3 #0 (#1) (#2) D0 #1 (#2) (#3) (#0) Last three data are masked.
Notes : DQS input must be continued till end of burst count even if some of laster data is masked.
- 31 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Mode Register Set Timing (CL=3, BL=2)
0 CK CK
IRC = 5 cycles
256Mb Network-DRAM
1
2
3
4
5
6
7
8
9
10
11
IRCS = 5 cycles
Command
RDA
LAL
DESL
IRAS = 4 cycles
RDA
MRS
DESL
RDA or WRA
IRCD = 1 cycle
IRCD = 1 cycle
A14 to A0 BA0, BA1
BA,UA
LA
X
Valid
(Op-Code)
X
BA,UA
DQS (Output)
Hi-Z
Hi-Z
CL = 3 Hi-Z Hi-Z
DQ (Output)
Q0 Q1
Power Down Timing (CL=3, BL=2)
0 CK CK 1 2 3 4 5 6 7 n-1 n n+1 n+2
IPDA = 1 cycles
Command
RDA
LAL
DESL
tIH tIS IPD = 1 cycle
X
DESL
RDA or WRA
IRCD = 1 cycle
A14 to A0 BA0, BA1
tQPDH Hi-Z Hi-Z
tPDEX
DQS (Output)
CL = 3
DQ (Output)
Hi-Z
Q0 Q1
Hi-Z
Power Down Entry
Power Down Exit
Note : "x" is don't care. IPD is defined from the first clock rising edage after PD is brought to "Low". IPDA is defined from the first clock rising edage after PD is brought to "High". PD must be kept "High" level until end of Burst data output. PD should be brought to high within tREFI(max) to maintain the data written into cell.
- 32 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Power Down Timing (CL=4)
Write cycle to Power Down Mode
0
CLK CLK
256Mb Network-DRAM
1
2
3
4
5
6
7
8
9
n-1
n
n+1
n+2
IRDA = 1 cycle
Command
WRA
LAL
DESL tIH tIS IPD = 1 cycle
x
DESL
RDA or WRA
PD

WL=3
2 clock cycles
tPDEX
IRC(min), tREFI(max) DQS (Input) BL=4 DQ (Input) Hi-Z D0 D1 D2 D3 Hi-Z Hi-Z Hi-Z

DQS (Input) BL=2 DQ (Input)
Hi-Z
Hi-Z

Hi-Z
D0
D1
Hi-Z
Power Down Entry
Power Down Exit
Note : "x" is don't care. PD must be kept "High" level until WL+2 clock cycles from LAL command. PD should be brought to high within tREFI(max) to maintain the data written into cell.
- 33 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Auto-Refresh Timing (CL=3, BL=4)
0 CK CK
IRC = 5 cycles
256Mb Network-DRAM
1
2
3
4
5
6
7
8
9
10
11
~
IREFC = 15 cycles RDA or WRA LAL or MRS or REF
Command
RDA
LAL
DESL
IRAS = 4 cycles
WRA
REF
DESL
IRCD = 1 cycle
IRCD = 1 cycle
~
DQS (Output)
Hi-Z
Hi-Z
CL = 3
~
DQ (Output)
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
Note : In case of CL=3, IREFC must be meet 15 clock cycles. When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh command specified by tREFI must be satisfied. tREFI is average Interval time in 8 Refresh cycles that is sampled randomly.
t1
CK
WRA REF
t2
t3
t7
t8
tREFI =
tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area than Read/Write operation.
~ ~
WRA REF
Total time of 8 Refresh cycle 8
~
WRA REF
8 Refresh Cycle
=
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~ ~
t1 + t2 + t3 + t4 + t5+ t6+ t 7+ t8
8
~ ~
WRA REF
REV. 0.7 Aug. 2003
~ ~
WRA REF
K4C5608/1638C
Self-Refresh Entry Timing
0 CK CK Command
IRCD = 1 cycle IREFC
256Mb Network-DRAM
2 3 4 5 m-1 m m+1
1
~~~~
~
X *1
WRA
REF
DESL Auto Refresh
tFPDL(min) tFPDL(max)
~~
PD
tQPDH
Self Refresh Entry
IPDV*2 Hi-Z ICKD = 16 cycleS *3
DQS (Output)
~
~
DQ (Output)
Qx
Hi-Z
Note : 1. "X" is don't care. 2. PD msut be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self Refresh mode When PD is brought to "Low" after IPDV, Network-DRAM perform Auto Refresh and enter Power down mode. 3. It is desirable that clock input is continued at least 16 clock cycles from REF command even though PD is brought to "Low" for Self-Refresh Entry.
Self-Refresh Exit Timing
0 CK CK 1 2 m-1 m m+1 m+2 n-1 n n+1 p-1 p
~ ~
~
IREFC
~ ~
IREFC
Command
X*1
DESL*3
IPDA = 1 cycle *4
WRA*5
REF*5
DESL
Command Command (1st)*6 (2nd)*6 IRCD = 1 cycle
~
RDA*7
LAL*7
IRCD = 1 cycle
~ ~
~ ~
~ ~
PD
tPDEX
ILOCK
~ ~
~ ~
~ ~
DQS (Output)
Hi-Z
~ ~
~ ~
~ ~
DQ (Output)
Hi-Z
Self-Refresh Exit Note : 1. "X" is don't care., 2. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode. 3. DESL command must be asserted during IREFC after PD is brought to "High". 4. IPDA is defined from the first clock rising edge after PD is brought to "High". 5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 6. Any command (except Read command) can be issued after IREFC. 7. Read command (RDA+LAL) can be issued after ILOCK.
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REV. 0.7 Aug. 2003
K4C5608/1638C
Function Description
Network-DRAM
256Mb Network-DRAM
The Network-DRAM is Double Data Rate (DDR) operating. The Network-DRAM is competent to perform fast random core access, low latency, low consumption and high-speed data bandwidth.
Pin Functions
Clock Inputs : CK & CK
The CK and CK inputs are used as the reference for synchronus operation. CK is master clock input. The CS, FN and all address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK. The DQS and DQ and DQ output data are referenced to the crossing point of CK and CK. The timing reference point for the differential clock is when the CK and CK signals cross during a transition.
Power Down : PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being performed.
Chip Select & Function Control : CS & FN
The CS and FN inputs are a control aignal for forming the operation commands on Network-DRAM. Each operation mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs.
Bank Addresses : BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for the operation. BA0 Bank #0 Bank #1 Bank #2 Bank #3 0 1 0 1 BA1 0 0 1 1
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REV. 0.7 Aug. 2003
K4C5608/1638C
Functional Description (Continued)
Address Inputs : A0 to A14
256Mb Network-DRAM
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle.
Upper Address K4C560838C-TC K4C561638C-TC A0 to A14 A0 to A14
Lower Address A0 to A7 A0 to A6
Data Input/Output : DQ0 to DQ7 or DQ15
The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal. The output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal.
Data Strobe : DQS or LDQS, UDQS
The DQS is bi-directional signal. Both edges of DQS are used as the reference of data input or output. The LDQS is allotted for Lower Byte (DQ0 to DQ7) Data. The UDQS is allotted for Upper Byte(DQ8 to DQ15) Data. In write operation, the DQS used as an input signal is utilized for a latch of write data. In read operation, the DQS that is an output signal provides the read data strobe.
Power Supply : Vdd, VddQ, Vss, VssQ
Vdd and Vss are supply pins for memory core and peripheral circuits. VddQ and VssQ are power supply pins for the output buffer.
Reference Voltage : VREF
VREF is reference voltage for all input signals.
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REV. 0.7 Aug. 2003
K4C5608/1638C
Functional Description (Continued)
Command Functions and Operations
256Mb Network-DRAM
K4C5608/1638C-TC are introduced the two consccutive command input method. Therefore, except for Power Down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out sequentially synchroniaing with the both edges of DQS output signal (Burst Read Operation). The initial valid read data appears after CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back automatically to the idle state after IRC.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DQS input signal (Burst Write Operation). The data and DQS inputs have to be asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The write data length is set by the VW in the LAL command. The DQS have to be provided for a burst length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the idle state after IRC.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
K4C560838/1638C-TC are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all outputs are in Hi-z states. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is specified by IREFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh, Auto-Refresh command has to be issued within once for every 7.8us by the maximum In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2us (8x400ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD="L")
It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an internal timer. When all banks are in the idle state and all outputs are in Hi-z states, the K4C560838/1638C-TC become Self-Refresh mode by issuing the SelfRefresh command. PD has to be brought to "Low" within tFPDL from the REF command following to the WRA command for a SelfRefresh mode entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 7.8us after the latest Auto-Refresh command. Once the device enters Self-Refresh mode, the DESL command must be continued for IREFC period. In addition, it is desirable that clock input is kept in ICKD period. The device is in Self-Refresh mode as long as PD held "Low". During Self-Refresh mode, all input and output buffers except for PD are disabled, therefore the power dissipation lowers. Regarding a SelfRefresh mode exit, PD has to be changed over from "Low" to "High" along with the DESL command, and the DESL command has to be continuously issued in the number of clocks specified by IREFC. The Self-Refresh exit function is asynchronous operation. It is required that one Auto-Refresh command is issued to avoid the violence of the refresh period just after IREFC from Self-Refresh exit.
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REV. 0.7 Aug. 2003
K4C5608/1638C
Power Down Mode( PD="L" )
256Mb Network-DRAM
When all banks are in the idle state and all outputs are in Hi-Z states, the K4C560838/1638C-TC become Power Down Mode by asserting PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD are disabled after specified time. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued at next CK rising edge after PD goes high. The Power Down exit function is asynchronous operation.
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The K4C560838/1638C-TC have two mode registers. These are Regule and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 in the MRS command.The Regular Mode Register designates the operation mode for a read or write cycle. The Regular Mode Register has four function fields. The four fields are as follows : (R-1) Burst Length field to set the length of burst data (R-2) Burst Type field to designate the lower address access sequence in a burst cycle (R-3) CAS Latency field to set the access time in clock cycle (R-4) Test Mode field to use for supplier only. The Extended Mode Register has two function fields. The two fields are as follows: (E-1) DLL Switch field to choose either DLL enable or DLL disable (E-2) Output Driver Impedance Control field. Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper operation.
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REV. 0.7 Aug. 2003
K4C5608/1638C
Functional Description (Continued)
* Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
256Mb Network-DRAM
BA1 0 0 1
BA0 0 1 X
A14 - A0 Regular MRS cycle Extended MRS cycle Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2 or 4 words. A2 0 0 0 0 1 A1 0 0 1 1 X A0 0 1 0 1 X Burst Length Reserved 2 words 4 words Reserved Reserved
(R-2) Burst Type field (A3) This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words. A3 0 1 Burst Type Sequential Interleave
* Addressing sequence of Sequential mode (A3) A column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. The address is varied by the Burst Length as the following.
CAS Latency = 2 CK CK Command DQS RDA LAL
DQ
Data 0 Data 1 Data 2 Data 3
Addressing sequence for Sequential mode Data Data 0 Data 1 Data 2 Data 3 Access Address n n+1 n+2 n+3 Burst Length 2 words (Address bits is LA0) not carried from LA0 to LA1 4 words(Address bits is LA1, LA0) not carried from LA0 to LA1 - 40 -
REV. 0.7 Aug. 2003
K4C5608/1638C
Functional Description (Continued)
256Mb Network-DRAM
* Addressing sequence of Inteleave mode A column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. Addressing sequence for Interleave mode Data Data 0 Data 1 Data 2 Data 3 Access Address ...A8 A7 A6 A5 A4 A3 A2 A1 A0 ...A8 A7 A6 A5 A4 A3 A2 A1 A0 ...A8 A7 A6 A5 A4 A3 A2 A1 A0 ...A8 A7 A6 A5 A4 A3 A2 A1 A0 2 words 4 words Burst Length
(R-3) CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to the first data read. The minimum values of CAS Latency depends on the frequency of CK. In a write mode, the place of clock which should input write data is CAS Latency cycles - 1.
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved Reserved 3 4 Reserved Reserved Reserved
(R-4) Test Mode field (A7) This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation. (R-5) Reserved field in the Regular Mode Register * Reserved bits (A8 to A14) These bits are reserved for future operations. They must be set to "0" for normal operation.
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REV. 0.7 Aug. 2003
K4C5608/1638C
Functional Description (Continued)
Extended Mode Register Fields
256Mb Network-DRAM
(E-1) DLL Switch field (A0) This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled. (E-2) Output Driver Impedance Control field (A1/A0) This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. A6 0 0 1 1 A1 0 1 0 1 Output Driver Impedance Control Normal Output Driver Strong Output Driver Weaker Output Driver Weakest Output Driver
(E-3) Reserved field (A2 to A5, A7 to A14) These bits are reserved for future operations and must be set to "0" for normal operation.
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REV. 0.7 Aug. 2003

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